module tb();

  real half_period = 10.0;
  
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire [3:0]            cnt;                    // From dut of digital_top.v
  // End of automatics
  
  //
  // clk, rst
  //
  reg clk;
  reg rst_n;
  initial 
    begin
      clk = 1'b0;
      forever
        #(half_period) clk = ~clk;
    end

  initial
    begin
      rst_n = 1'b0;
      #101 rst_n = 1'b1;
    end
  
  //
  // timeout 1 second
  //
  initial 
    begin
      #1s;
      $display("TIMEOUT 1s, simulation exit.");
      $finish();
    end

  //
  // dump fsdb
  //
  initial 
    begin
      $fsdbDumpfile("tb.fsdb");
      $fsdbDumpvars(0, tb);
    end

  //
  // user testcase
  //
`include "testcase.sv"

  //
  // inst design top
  //
  digital_top dut
    (/*AUTOINST*/
     // Outputs
     .cnt                               (cnt[3:0]),
     // Inputs
     .clk                               (clk),
     .rst_n                             (rst_n));
  
endmodule // tb

// Local Variables:
// verilog-library-directories:("." "../../rtl")
// End:

